ASIC Manufacturing Process

Tailored for Mixed Signal Performance

STA’s ASIC design processes are optimized for mixed signal and analog performance. We use facilities all over the world to assure high quality, cost effective fabrication capability. From low voltage battery applications to higher voltage industrial interface requirements, we provide our customers with silicon solutions that meet their budget, specifications and delivery schedules.

Process Features

visualization of asic design process

  • 0.7 to 700V CMOS and BiCMOS 20nm, 90nm, 180nm, 350nm, 0.6μm, 0.8μm, 1.0μm and 2.0μm
  • Silicon On Insulator (SOI) with low RON and DMOS
  • Low TC, Poly to Poly Matched Capacitors
  • High volume MIM Capacitors
  • Low TC, Matched High Impedance Poly Resistors
  • Zero TC, Matched Low Impedance Poly Resistors
  • Low TC, Matched CAP Resistors
  • Positive TC Matched Resistors
  • Negative TC Matched Resistors
  • Inductors
  • Poly fuse
  • Zener Zap
  • Optical
  • MEMS
  • ROM
  • SRAM
  • DRAM