A Guide To ASIC Design

In this article, we’ll go over the ASIC design modeling process, gate-level physical design, and its specifications.

Table Of Contents

  1. What Is ASIC Design
  2. ASIC Specification
  3. Logic Design
  4. Physical Design
  5. Additional Resources

What Is ASIC Design?

ASIC design is a methodology of cost and size reduction of an electronic circuit, product or system through miniaturization and integration of individual components and their functionality into a single element – an Application Specific Integrated Circuit (ASIC).

An electronic product commonly consists of many integrated circuits (ICs) which are interconnected together to perform a particular function. For example, a 1980’s smoke detector was built entirely of general-purpose ICs, such as amplifiers, comparators, regulators and discrete components such as resistors and capacitors.

It was expensive (component cost and assembly cost) and bulky (all those components required space). As competition intensified, the requirement for lower cost and smaller size drove the need for consolidation and integration of all those individual components into a single ASIC, reducing not only overall cost and size of the smoke detector but also improving its reliability (fewer parts, fewer things to go wrong).

Recently, VLSI CMOS has played a crucial role in placing millions of transistors on a single chip, providing digital system designers with an ability to implement a vast number of gates with complex functionality on a single IC.


According to Moore’s Law, the number of gates or transistors doubles after every 18 months and is growing to extremely high densities per IC. Rapidly growing technology in logic, parallelization, CAD tools, and memory promises continued advancement in the next 15 years. With the help of CAD tools, high-level descriptions can be translated into specific functions such as registers, microcontrollers, ALU, control units and more.

Detail of Silicon Wafer Containing Microchips

Modern ASICs combine multiple complex blocks in a single package, including analog elements such as an amplifier, ADC, PLL and digital elements such as a microcontroller, OTP, ROM, EEPROM, RAM, and other building blocks. These types of ICs are known as system on chip (SoC). The analog section of the ASIC is designed using primarily transistor-level design techniques and manual layout processes. The digital section of the chip is designed primarily using hardware description languages such as VHDL/Verilog followed by automated Place and Route (PnR) layout process.

There are three types of ASIC chip designs:

  • Full Custom Design
  • Semi-Custom Design
  • Programmable ASIC

Some examples of ASIC chips include chips in the consumer, medical, automotive, and industrial sectors. ICs that are not ASICs are general-purpose ICs such as voltage regulators, stand-alone memories (EEPROM, RAM)

Year  1995  1998  2001  2004  2007  2010
 Feature size (μm) 0.35 0.25 0.18 0.13 0.10 0.07
  5M 14M 26M 50M 210M 430M
DRAM bits/chip 64M 256M 1G 4G 16G 64G
Number of I/O 900 1350 2000 2600 3600 4800
Chip-to-board speed 150 200 250 300 375 475
Maximum number of wiring levels (logic) 4-5 5 5-6 6 6-7 7-8
On-chip speed (MHz) 300 450 600 800 1000 1100


The evolution of VLSI as told by the Semiconductor Industries Association

What Is A Specification?

An ASIC specification is a document that lists how a device needs to function and perform in various operational situations such as tithe specification phase is an extremely significant part of the design and development process. As technology becomes more advanced and entrenched in every aspect of life, customers are expecting new features and design improvements from their devices, including high-speed processing and low power consumption. A top-down design approach is employed to navigate and manage complexities of the ASIC design process, and as a first step, dictates the development of a proper detailed specification. A thoroughly crafted working specification helps guide the design process, with the project less prone to errors disruptive to project schedule and cost.

It is very important that an expert in ASIC system design assists customers in developing system architecture and specifications. This extensive process takes around 2 to 6 weeks depending upon the complexity of the application requirements. The specification process is followed by:

  1. Reviewing the block diagram, system schematics, and specifications
  2. Developing an understanding related to design problems, operating environment, and challenges
  3. Making a decision related to the final product, not only ASICs
  4. Determining if any certification is required in the product such as IEC, TS compliance
  5. Designing or compiling the ASIC block diagram with full functional components, specifications, and pinout
  6. Deciding board-level architectural trade-offs that lead to the most cost-effective silicon integration

What Is Logic Design?

Logic design for an ASIC begins with the design team analyzing the functional specification in order to define and create a logic design architecture. The architecture definition includes a block diagram that provides details about functional relationships between digital logic such as, finite state machines, combinational logic, sequential logic, processors, memories, data path design, communication buses, and the connections between them.

Once the architecture definition is in place, the next step is to describe detailed functionality of the blocks and connection between the respective functional blocks. Description of logic design functionality is accomplished using either a graphical depiction (schematic), or more commonly, and particularly with large systems, a purpose-specific hardware definition language (HDL code) such as Verilog and VHDL.

HDL code can be written at different levels of abstraction from transistor level logic depending on the chosen design flow and development needs. Very large systems and or complicated systems will start at the behavioral level. Behavioral is the highest level of abstraction from a gate to gate-level description and is often coded in languages such as System Verilog, Verilog, VHDL, and C. Behavioral level coding generally cannot be directly synthesized to gate-level logic but is useful for modeling and verification.

Register-Transfer Level (RTL) coding is abstracted from a gate-level description for increased coding efficiency but is synthesizable with EDA (Electronic Design Automation) tools to produce gate level and ultimately transistor-level implementations. RTL code describes the desired hardware by implying logic, by defining flip-flops, latches, and how data is transferred between them. Synthesis of RTL code utilizes the power of advanced EDA tool capabilities to, create, alter, and optimize the logic used for implementation, but not functional behavior.

Gate level coding is the least abstracted from transistor level logic. Gate level coding describes the design using the base logic gates, NAND, NOR, AND, OR, MUX, FLIP-FLOP. It does not need to be synthesized and has the lowest level of abstraction. Gate level coding is useful for smaller less complicated designs or designs that require very specific implementation for performance but does not offer the design efficiency that comes with higher levels of abstraction in concert with sophisticated EDA (Electronic Design Automation) tools.

The design team will also provide an estimate of the on-die block area required for implementation, and other details affecting the cost and power usage of the digital logic system.


The logical design is verified for matching of original design intent and implementation at several stages throughout the design process to ensure an accurate successful ASIC outcome. The verification process includes applying test cases to the detailed design description and confirming that the expected behavior is achieved. Verification is also carried out at additional stages of the design, using sophisticated EDA tools to compare gate-level netlists to the design description and actual layout implementation to the synthesized netlist. If any verification test fails along the way, the design is sent back for correction to the design department responsible for that particular part of the implementation. Continual design and implementation verification throughout the development process catch errors and design deficiencies before they become costly time-consuming mistakes.

Design Synthesis

Design synthesis is the process of translating the logical design into a gate-level netlist that can then be implemented as a physical silicon structure. The logical design and its detailed description are technology-independent until the synthesis process. The synthesis process uses advanced EDA tools that are aware of the capabilities and limitations of the target technology (FAB process) that the high-level abstracted design is being ported to. Design synthesis output is technology-dependent, tailored to the target ASIC process.


Physical Design Flow

Image Courtesy of Wikimedia Commons

What Is Physical Design?

Physical design (also known as back-end design) is the process of converting the gate-level netlist produced at synthesis into functional ASIC hardware. Physical design steps include floor planning, power planning, partitioning, placement, routing, clock tree synthesis, final verification, and export as a GDSII file to the fabrication facility for construction. A number of high-level EDA tools from various vendors such as Cadence, Synopsis, Magma, Mentor Graphics are available to facilitate back-end design. They each have their strengths and weaknesses and are sometimes used in concert to achieve an efficient implementation path with optimal results.


Floorplanning is the process of placing functional blocks in the chip area so as to allocate routing areas between them, plan for critical power and ground connections, and determine Input / Output (IO) pad locations. A good floorplan will balance design constraints to minimize total die area, optimize signal routing channels for ease of layout and signal performance, and relative placement of functional blocks to minimize interference and preserve signal integrity. Careful floorplanning is key to how well the rest of the physical design process flows.


Partitioning (logical partitioning) is the process of dividing the chip into small blocks. The objective of partitioning is to make the functional block easier for placement and routing. This step can be done in the logical design phase when the design team divides the entire design into sub-blocks for development, or at the physical design (back-end) phase to aid in place and route activities focused on routing channels, signal integrity, and dies utilization.

Power Planning

Power planning takes into account the energy usage of each block, individual voltage supplies, ground paths, and interaction between them. Power Planning is one of the most important stages in Physical design. It is actually an integral part of the floorplanning process, but due to its significance in ASIC performance and function, it is often addressed as a separate stage of consideration.

During power planning, location for ground and power rings, cross die trunks, and isolated routes for sensitive circuits are allocated. Constraints for internal core ASIC circuitry and I/O cell power management are treated separately because they often have different demands. Special power pads are used for positive supply, ground, and negative supply. Multiple power and ground pads are often used to reduce the series resistivity and inductive impedance that affects, voltage drop, signal integrity, and high-speed performance.


Placement is the process of dividing the chip into smaller blocks by placing the correct position to standard cells with none overlapping on the chip. Placement is performed in four optimization phases: pre-placement, in-placement, and post-placement before and after clock tree synthesis.

Clock Tree Synthesis

Clock tree synthesis is the process of ensuring that clock signals are distributed evenly to all sequential elements in a design with the primary objective of preventing clock timing-related errors. Clocking of gates in high-speed designs are subject errors as a result of the clock edge not arriving at the exact time it is expected relative to when it arrived at other parts of the circuit. This timing error is called clock skew and is dependant on a number of variables both in the original design and in physical implementation.

Clock tree synthesis performed during the physical design process considers the effects of place and route, channel impedance, parasitic loads, etc. Then through the insertion of buffers or inverters along the clock paths to minimize or balance skew of important clock signal chains, build a clock tree that achieves proper timing across the entire design.


Routing is the process of connecting macros, standard cells, I/O ports, power, and the clock physically with metal traces. Routing is divided into two steps: global and detailed routing. In global routing, trace or wire length, and route channel congestion are estimated. In detailed routing, the actual connections within each block are made.


Design For Manufacture is paramount to achieve production yield and part reliability. As ASIC designs become larger and more complex and process technologies become more intricate, it is important that key factors such as process limitations, parameter repeatability, environmental and signal stresses are considered and factored to increase the probability of successful part to part results. Factoring of process and use constraints to increase yield, decrease test time, and other processing concerns are what is termed design-for-manufacture (DFM). DFM can often be the difference between a successful ASIC project that meets cost, reliability, and production goals versus one that falls short.

Additional Resources

Analog vs. Digital – What’s the Difference?

We live in an analog world, all that we see, all that we hear, all that we taste is analog. Digital is our best approximation of the analog world, one sample at a time. If our samples are close enough together, our approximation is almost perfect, if our samples are further apart we start missing details.

Digital is on/off. Analog is on/off and all the possibilities between. Take light as an example.

A simple toggle light switch (digital) turns the light full-on or off, light or no light. A slider lighting control (analog) allows the light to range anywhere from full-on to off and all the range of brightness between.

Since analog contains all the possibilities between on and off, it represents a great deal more information than just on/off. So if all the information is in analog, why not always work strictly with analog signals?

Because processing data, making decisions, and storing information is in general more easily and efficiently done by digital controllers and computers using digital signals. Because of this, the analog world is often converted to digital when making complex decisions.

However, to shift from operating in the analog world to digital requires some compromise, loss of information. Conversion from analog to digital is done with a series of single points of data that do not represent all the possibilities of analog, but a bunch of them.

The number of single points used to represent the analog world depends on how closely the digital representation needs to match. Requirement for a very close match can result in a huge number of data points to the point of straining capability of the digital processing capability.

Therefore a balance is required and there is cause for both analog and digital processing to be used.

Is analog better than digital?

Analog and digital both have their place and the decision to use one, the other, or both is based on a number of factors

  • Cost
  • Accuracy
  • Processing requirements
  • Flexibility
  • System demands of using one vs the other

Nature is an analog system, our brain processes all inputs, stores information and makes decision in analog domain, unfortunately we do not yet have the technology that could fully emulate nature’s analog performance. Until we do, we are limited to a hybrid solution.

We use analog technology as an interface between the real world around us and digital world that computers can interpret and process. We receive concert sound using analog technology, we sample this sound to produce its digital representation. We store this sound in digital domain, iPod, and when we want to hear playback of previously stored track, we use analog technology to translate stored signal from digital world back to analog world, our ears can understand.

ASIC vs. FPGA: Which To Choose & Why

In this post, we’ll compare ASIC vs. FPGA and help you determine which one is the best technology for you. ASIC and FPGA are both integrated circuit technologies. ASIC stands for Application-Specific Integrated Circuit and is customized for a specific applications’ need. FPGA stands for Field Programmable Gate Array and can be programmed in the field. Silicon area use is a driving factor in production part cost.

What is an ASIC?

ASIC architecture can range from a Gate Array , were predefined building blocks are selectively interconnected during layout process (lower development cost, higher unit price), to a full custom implementation where each transistor is optimized for a required function (higher development cost, lower unit price). Since an ASIC only includes the needed resources required to accomplish the design task, silicon area is optimized, making ASIC implementations the lowest cost solution in medium to high volume applications. Once the ASIC design is complete, the ASIC must then be manufactured in specialized fabrication facilities, which takes up to 12 weeks for engineering prototypes and 20 weeks for fully assembled and tested production ASIC.

What is an FPGA?

Now let’s compare FPGAs vs ASICs. FPGA is an acronym for Field Programmable Gate Array.  Similar to ASIC Gate Array architecture, an FPGA consists of predefined hardware resources.  Unlike an ASIC gate array, FPGA hardware resources can be programmed (connected or disconnected from each other) in the field with a simple programming device.  Once a digital design is completed, the Field Programmable Gate Array can be immediately programmed and deployed. However, such incredible flexibility is not free, FPGA parts have a very high production unit price as compared to an ASIC unit price.  FPGA technology is an excellent prototyping vehicle for digital logic and a perfect solution for low volume products.

ASIC Vs. FPGA: Which One Should You Choose?

Although ASIC implementations require more up front design cost and longer fabrication time than FPGA, ASIC offers a number of important advantages beyond just a lower production unit cost.  An ASIC can integrate valuable technology not available in an FPGA, including, analog functionality for signal conditioning and acquisition of sensor input, asynchronous logic for use of smaller footprint and lower system clock speed, power supply management, blocks optimized for specific function such as power supply control, low power functionality, and many other optimizations that add value to a design.

ASIC vs FPGA Comparison

ASIC – Application Specific Integrated Circuit FPGA – Field Programmable Gate Array
Low unit cost High unit cost
High development cost Low development cost
Long manufacturing cycle Short manufacturing cycle
Low power dissipation High power dissipation
Small footprint and multiple package options Large footprint and limited package options
Analog, Digital, and Mixed-Signal technology options Digital with limited Analog IP blocks



Credit Card Reader Application

STA’s Mixed Signal ASIC Technology Powers Wireless Credit Card Reader

credit card readerHandheld PCs, PDAs and smart cell phones are showing up in new applications every day. These new products are made possible by the adoption of wireless technology and the internet. Taxi and delivery services, vendors at fairs and swap meets and many other mobile merchants are now able to accept credit cards in the field.

Semtek Corp, a San Diego based company that manufactures credit card readers, was developing a new product. “Our new reader had to be small, very low power and low cost,” remarked Dennis Mos, VP Sales and Marketing at Semtek.

Size, power and cost are all benefits of ASIC technology; however, developing an ASIC, particularly a Mixed Signal ASIC, can be expensive and time consuming. Such an undertaking may prove especially risky for new product like Semtek’s wireless credit card reader. Many engineering managers are of the mind that ASIC’s are best left to the “Big Boys.” And considering the high cost of tools, masks and fabrication they are probably correct, but not completely.

A unique ASIC process developed by System To ASIC provided Semtek with the Mixed-Signal technology they needed, at a cost far less than that of standard cells or a full custom IC. According to Douglas Shorb, Vice President of Sales at System to ASIC, Inc. (STA) our customers do not have to pay exorbitant development cost or inflated unit prices because only the last few steps of the manufacturing process are custom. This means that no single customer bears the entire design and manufacturing cost.

At first Semtek, like many other companies, couldn’t imagine that an ASIC would work for them. Having just started production on the new credit card reader, the initial expectation was that somewhere around 50,000 units would be manufactured in the first year. While there were a lot of components on the tightly packed PCB, and power consumption was higher than they had wanted, the new product would do well in the market, and cost reduction would be considered after production volumes increased.

“It takes quite a few analog parts to read a three track credit card” explains Clay von Mueller, Vice President of Engineering at Semtek. After discussing the design with the team at STA, Semtek decided to take a closer look at using an ASIC in their new product. The goal was to eliminate 55 components, including 10 amplifiers, reducing cost by enough that the project could pay for itself in its first year.

“Developing this ASIC was much easer than I expected,” notes Von Mueller. “We gave System To ASIC a copy of the schematic and our wish list. Within a few days we received a block diagram for our new chip, including the development cost, unit price, schedule and even an ROI calculation to help with the financial analysis.” Controlling every aspect of the chip’s operation was critical in meeting Semtek’s low power requirements. Taking advantage of the fact that credit card readers need to be fully powered only during actual card swipe, most sections of the chip were turned off during sleep mode, while others were placed in a low-power state in order to conserve energy.

With sleep current under control, the team at STA reinvested some of the saved power back into higher performance amplifiers and detection circuitry. Any trade-off between peak performance and stand-by current did not present an issue due to the fact that credit card readers consume almost 95% of their power while sleeping.

System To ASIC delivered prototypes on schedule, just under 4 months. “Our new chip worked right out of the box, sleep current dropped by over 90%, detection accuracy and speed have significantly improved, the ASIC outperformed design expectations in every category” recalls Von Mueller.

Semtek’s new chip allowed the removal of fifty five (55) electronic components, two (2) connectors and an entire PCB assembly. Overall, the ASIC reduced the cost of components by over $3.00, in addition to the savings from reduced manufacturing and test costs.

As promised, the ASIC came in on schedule exactly as quoted, and it paid for itself in less than 6 months. Semtek Innovative Solution has been acquired by VeriFone Systems, Inc.

Semtek Innovative Solution Corp.
System To ASIC , Inc. (STA)